随便记一点:初识aurora接口
sof_n:数据传输开始标志,低电平有效;
eof_n:数据传输结束标志,低电平有效;
*rdy_n:传输数据有效标志,低电平有效;
Status and Control Ports
reset/tx_ststem_reset/rx_system_reset
gt_reset:r. The gt_reset port should be asserted when the module is first powered up in hardware.
init_clk_in:The init_clk_in port is required because user_clk stops when
gt_reset is asserted. It is recommended that the frequency chosen for init_clk_in be lower than the GT Reference Clock input frequency.
tx_aligned,tx_bonded,tx_verify,rx_reset:与rx的对应接口相连
Only available in TX-only simplex dataflow mode and sideband as back channel core configuration.
Only available in RX-only simplex dataflow mode and sideband as back channel core configuration.
Status and Control Ports (Cont’d)
暂空,和上节表对应
Full-Duplex Status and Control Ports
Cont’d是续的意思,这里是续表
lane_up总线指示通道中的哪些车道已完成车道初始化过程。该信号可用于帮助调试多通道信道中的设备问题
channel_up只有在核心完成整个初始化过程后才会断言
在断言channel_up之前无法接收数据。只能使用用户界面上的m_axi_rx_tvalid信号来限定传入的数据。
channel_up可以倒置,用于重置驱动全双工通道TX侧的模块,因为直到channel_up之后才能发生传输
如果在数据接收前需要重置用户应用程序模块,则可以倒置并使用其中一个lane_up信号。在断言所有lane_up信号后才能接收数据
Simplex Cores
This interface includes the serial I/O ports of the transceivers, and the control and status
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